Power semiconductor switches are currently being used increasingly in converter technology and particularly in converter circuits for switching three voltage levels. Such a converter circuit for switching three voltage levels is specified in DE 699 02 227 T2. FIG. 1a shows a converter subsystem for a phase of the converter circuit, where the converter subsystem shown in FIG. 1a corresponds to a converter subsystem from DE 699 02 227 T2. As FIG. 1a shows, the converter circuit is provided with a DC voltage circuit formed by two series-connected capacitors, the DC voltage circuit having a first principal connection and a second principal connection and a subconnection formed by the two adjacent and interconnected capacitors. The capacitance value of the two capacitors is usually chosen to be the same. The first principal connection and the second principal connection have a DC voltage applied between them, with half the DC voltage UDC/2 therefore being applied between the first principal connection and the subconnection, i.e. to the one capacitor, and half the DC the DC voltage likewise being applied between the subconnection and the second principal connection, i.e. to the other capacitor. The DC voltage is denoted by UDC in FIG. 1a. 
Each converter subsystem in the converter circuit from DE 699 02 227 T2 or from FIG. 1a has a first, a second, a third, a fourth, a fifth and a sixth power semiconductor switch, the first, second, third and fourth power semiconductor switches being connected in series and the first power semiconductor switch being connected to the first principal connection and the fourth power semiconductor switch being connected to the second principal connection. The junction between the second power semiconductor switch and the third power semiconductor switch forms a phase connection. In addition, the fifth and sixth power semiconductor switches are connected in series and form a clamping switching group, the junction between the fifth power semiconductor switch and the sixth power semiconductor switch being connected to the subconnection, the fifth power semiconductor switch being connected to the junction between the first power semiconductor switch and the second power semiconductor switch, and the sixth power semiconductor switch being connected to the junction between the third power semiconductor switch and the fourth power semiconductor switch. The first, second, third and fourth power semiconductor switches are actuatable bidirectional power semiconductor switches, each formed by an insulated gate bipolar transistor (IGBT) and by a diode connected back-to-back with the bipolar transistor. The fifth and sixth power semiconductor switches in DE 699 02 227 T2 are nonactuatable unidirectional power semiconductor switches, each formed by a diode. In this case, the fifth and sixth power semiconductor switches form a passive clamping switching group. However, it is also conceivable for the fifth and sixth power semiconductor switches to be actuatable bidirectional power semiconductor switches, each formed by an insulated gate bipolar transistor (IGBT) and by a diode connected back-to-back with the bipolar transistor. In that case, the fifth and sixth power semiconductor switches form an active clamping switching group.
DE 699 02 227 T2 also specifies a method for fault handling in a converter circuit for switching three voltage levels. First of all, in the event of a fault occurring, for example on account of a faulty power semiconductor switch, it is detected whether the fault is in a top fault current path or in a bottom fault current path in the converter circuit. In this context, the top fault current path is defined by a fault current through the first, second, third and sixth power semiconductor switches or by a fault current through the first and fifth power semiconductor switches. In addition, the bottom fault current path is defined by a fault current through the second, third, fourth and fifth power semiconductor switches or by a fault current through the fourth and sixth power semiconductor switches. For fault handling, a fault switching sequence is initially followed by the power semiconductor switch(es) which is/are in desaturation being turned off. This requires each power semiconductor switch being monitored for desaturation using a desaturation monitoring device. Such desaturation on the power semiconductor switch, particularly on the IGBT, occurs, by way of example, when a fault, such as a short, occurs in the principal current path, i.e. between the anode and the cathode or between the collector and the emitter of the IGBT. Other faults are naturally also conceivable. In such a fault situation, the current in the principal current path typically rises very quickly to a high current amplitude, which means that the current integral over time assumes inadmissibly high values. During this overcurrent which arises, the IGBT is driven to desaturation, with the anode/cathode voltage across the IGBT rising quickly, particularly to the value of the voltage which is to be connected. This achieves an extremely critical state for the IGBT: the IGBT firstly routes a high current (overcurrent) through the anode and the cathode in the principal current path. Secondly, a high anode/cathode voltage is simultaneously applied between the anode and the cathode of the IGBT. This results in an extremely high instantaneous power loss which can destroy the IGBT. When the desaturated power semiconductor switch(es) has/have been turned off, the power semiconductor switches are then switched on the basis of the fault switching sequence such that a phase short arises in each converter subsystem, i.e. the converter circuit is then shorted on each of its phases.
The short on all phases of the converter circuit from DE 699 02 227 T2 allows a short circuit current to be produced in the converter subsystem affected by the fault and in the other converter subsystems, however, said short circuit current placing a burden on the power semiconductor switches. A power semiconductor switch burdened in this manner can therefore age more quickly or can even be damaged, which means that the availability of the converter circuit is severely impaired or at worst is eliminated.
In addition, JP 11032426 discloses a method for fault handling in a converter circuit for switching three voltage levels. To avoid an overvoltage on one of the power semiconductor switches, detection of an overcurrent through the first and second power semiconductor switches and detection of an overcurrent through the third and fourth power semiconductor switches prompt first of all the first and fourth power semiconductor switches and then the second and third power semiconductor switches to be turned off.